Not applicable.
Not applicable.
1. Field of the Invention
The present invention relates generally to microprocessors for computer systems. More particularly, the present invention relates to measuring skew and jitter of various clocks of a microprocessor. More particularly still, the present invention relates to measuring the uncertainty window of a target clock signal caused by skew and jitter, the measurement made with circuits on the microprocessor die.
2. Background of the Invention
The trend in modem microprocessor design is to place increasing functionality onto the microprocessor die. Early microprocessors, for example, did not have onboard floating point units or onboard cache. In more recent times, it is rare to find a microprocessor manufacturer who does not incorporate a floating point unit and at least some cache on the microprocessor die. To some extent the incorporation of additional circuits on the microprocessor die has been made possible by advances in manufacturing technologies that allow semiconductor companies to shrink the size of the various electrical components created on the silicon substrates. Notwithstanding that manufacturers may now place more components in the same area than they could just a few years ago, the overall footprint of microprocessors has increased significantly as well. This increase in size, along with the incorporation of additional components within the microprocessor, creates problems in the distribution of clock signals throughout the microprocessor.
Electrical signals move from point to point in electrical conductors at a speed approaching that of the speed of light. While this speed of propagation is very fast, it is finite, and at the component spacings and clocking speeds of modem microprocessors (on the order of 1 Giga-Hertz or more), these finite speeds can cause timing problems between various clock domains or patches of a microprocessor. One timing problem associated with clock propagation speed is usually seen in the form of delays in the arrival of clock pulses, which is known in the industry as skew.
In the design of microprocessors, clock domains receive their clock signal through a distribution tree. That is, the clock signals propagate through many circuits, which may include devices such as clock buffers and delay locked loops, in their distribution about the microprocessor die. In its most fundamental form, any logic gate that the clock signal propagates through is simply one or more transistors. There may, however, be variations in transistor speeds across a microprocessor die caused by irregularities in doping and etching (device widths) during manufacture. Further, large die microprocessors may have temperature variations across the chip during operation. For example, there may be a significant localized temperature increase in the floating point unit of a microprocessor when executing floating point intensive operations These temperature variances may affect operational speeds of the transistors in the region of localized temperature increase. The localized temperature increases are sporadic and highly dependent upon the software executed by the microprocessor. Because of the variations in logic gate propagation speeds and the localized temperature increases, accurate prediction or design of the arrival of any particular clock signal is difficult. All these factors contribute to cause skew and jitter in the clock circuits distributed about the microprocessor.
For purposes of further explanation of the terms skew and jitter, reference is now made to FIG. 1A. FIG. 1A shows several clock pulses of an ideal clock signal. The waveform represented in FIG. 1A is ideal in the sense that it shows practically instantaneous rise and fall times between the high voltage state and the low voltage state. Plotted on the same axis is FIG. 1B, which shows two aspects of the skew and jitter problem faced by clock designers. In particular, the first rising edge 10 of the waveform of FIG. 1B is shown to be some finite amount of time after the first rising edge 12 of the waveform of FIG. 1A. In similar fashion, the first falling edge 14 of the waveform of FIG. 1B is shown to be a finite amount of time after the falling edge 16 of the corresponding waveform FIG. 1A. Thus, this first rise and fall of the waveform of FIG. 1B is exemplary of clock skew. As the FIGS. 1A and 1B imply, clock skew is a shifting of a measured waveform relative to a reference waveform.
The waveforms of FIG. 1A and FIG. 1B also show the idea of duty cycle jitter. In particular, the second rising edge 18 of the waveform of FIG. 1B is shown to be a finite amount of time after the rising edge 20 of the waveform 1A. However, the falling edge 22 of the waveform of FIG. 1B is shown to be in exact time alignment with the falling edge 24 of the waveform of FIG. 1A. Thus, the duty cycle (the ratio of a signal""s high voltage time to its low voltage time) has changed. Momentary changes in duty cycle may increase or decrease the duty cycle, as well as the rise and fall times of any particular clock pulse.
A microprocessor designer may not know precisely when a particular clock signal may arrive at a clock domain of the microprocessor relative to a master clock. Rather, and referring to FIG. 1C, the skew and jitter of a clock signal results in a fuzz or uncertainty window 26 within which a state transition (rising or falling edge) may occur. The uncertainty window represents the span of time within which a clock signal may make a state transition. Thus, what becomes important to a clock system designer is not when any one particular state transition occurs, but the width of uncertainty window 26 within which that rise or fall may occur.
Knowing the uncertainty window 26 is important to the microprocessor designer for many reasons. One reason may be the exchange of information between various clock domains of the microprocessor. In particular, in the exchange of information between clock domains of the microprocessor, it is important that data is asserted for a requisite amount of time such that the receiving device has the ability to read that information. Holding the information in its proper state is sometimes referred to as hold time. If the uncertainty window 26 becomes too wide, the resulting active time of any particular clock signal may become too short to allow the receiving clock domain to read and store the information. Thus, microprocessor designers need to know the width of the uncertainty window 26. The prior art, however, has been deficient in providing a system to make this measurement.
Two prior art techniques exist for measuring particular signals on a microprocessor die, including clock signals. Both methods involve machining through the bottom of the microprocessor silicon substrate to measure particular signals by observing their affect on hardware of the microprocessor. The first technique involves shining and infra-red (IR) lazer at the channel-drain region of metal oxide semiconductor (MOS) transistors in the signal chain of interest. This technique relies on the fact that the IR reflectivity caused by field and carrier effects in the PN junction between the drain and inversion layer change as the particular transistor switches on and off. Data gathering in this first technique must take place over several minutes. The second prior art approach gathers photons emitted from switching transistors. However, a transistor does not release a photon every time it operates, thus requiring the measurement procedure to extend over several hours.
Each of the two prior art techniques requires expensive equipment, elaborate die preparation, and highly trained people to run and maintain the equipment. Because of the time and expense associated with these two prior art techniques, they are generally only applicable as a design debug technique, and not as a manufacturing test technique.
Thus, what is needed in the art is a mechanism by which a clock designer can measure the uncertainty window of a clock signal on a microprocessor die without the need of expensive equipment or destructive test procedures.
The problems noted above are solved in large part by a structure and related method which measures the uncertainty window of clock signals on the microprocessor die using circuitry on the microprocessor die itself. In this way, no expensive equipment or destructive test procedures are required. More particularly, in the preferred embodiment, each cache region of the microprocessor has a jitter measurement circuit. This jitter measurement circuit is adapted to measure the uncertainty window of the clocks of those caches. An alternative embodiment may also measure the uncertainty window associated with other clock signals on the microprocessor by use of a multiplexer. The jitter measurement comprises a calibration unit, a delay unit and a measurement unit. Preferably, the calibration unit is used to establish an on-die time reference, and that time reference is used to calibrate various other portions of the jitter measurement circuit. The delay unit has a plurality of adjustable delay circuits. By coupling each of these adjustable delay circuits to a host clock, and setting the delay associated with each adjustable delay circuit different from the others, a plurality of reference clock signals having the same frequency but differing in phase relationship are created. In the preferred embodiment, four such reference clock signals are created. By defining time windows or bins between corresponding features of these reference clock signals, three time windows or bins are created. Because the delay circuit within each delay unit is adjustable, the time width of these windows or bins may be adjusted as necessary, and as part of the procedure for determining the uncertainty window. Preferably these four reference clock signals, and the clock signal to be measured, the target clock, are coupled to the measurement unit.
In the measurement unit, the reference clock signals and the target clock signals are compared. More particularly, the target clock signal is compared to each of the reference clock signals to determine whether that target clock signal makes a state transition before or after the particular reference clock signal. In this way, a determination is made regarding within which time window or bin the target clock signal makes its state transition. By running this comparison over several thousand clock cycles of the target clock signal, a pattern develops as to the outer boundaries of state transitions of the target clock.
The preferred embodiment also comprises software which is preferably executed by hardware other than the particular microprocessor whose clock signal uncertainty windows are being measured. By way of the scan chain communication, the external software may adjust the relative sizes of the various time bins, start and stop measurement runs, and read results from those measurement runs. It is envisioned that calculating an uncertainty window for any particular clock in the microprocessor will be an iterative process involving repeatedly measuring the target clock signal against the reference clock signals with a particular time window width, adjusting those widths based on the outcome of a particular measurement run, and repeating the steps as necessary until the width of the uncertainty window is determined.
In another related aspect, the various circuits on the microprocessor die need to be calibrated prior to any measurement run to determine the uncertainty window. The calibration unit, previously mentioned, preferably aids in the calibration by establishing a time reference on the microprocessor die. More particularly, in the preferred embodiment, the calibration unit determines the propagation speed of inverters on the microprocessor in relation to the period of the clock applied to the microprocessor. While the on-die circuitry may not know the frequency of the applied clock, preferably the external software does. By knowing how many inverter propagation delays fit within one complete period of the applied clock, the external software may therefore calculate the propagation delay time of any particular inverter. Relying on the fact that the propagation delay time of inverters on the microprocessor die is known, the calibration unit also creates a plurality of calibration time references having the same frequency, but shifted in phase by an amount of time equal to the propagation of two inverters. These two calibration signals are used to calibrate other adjustable or programmable portions of the on-die circuitry for measuring the uncertainty window. In particular, each adjustable delay circuit of each delay unit uses these calibration reference signals to determine the time-wise effect of each tap of the adjustable circuit. More particularly still, by phase-locking first to the first reference signal, and noting the number of taps to facilitate this phase lock, then phase-locking to the second calibration reference signal, and again noting the number of taps required to complete this lock, the external software, now knowing the time difference between the calibration reference signals, and the difference in the number of taps to have the adjustable delay circuits locked to each of these signals, may attribute the time difference between the calibration reference signals to the difference in the number of taps between locking to those two signals. In this way, the time value of each tap is determined, and this information is then preferably used during the measurement procedure in setting the width of the various time bins.